The following applications are related to the present application, and are hereby incorporated by reference as though fully and completely set forth herein:
Ser. No. 08/340,667 titled xe2x80x9cIntegrated Video and Memory Controller With Data Processing and Graphical Processing Capabilitiesxe2x80x9d and filed Nov. 16, 1994;
Ser. No. 08/463,106 titled xe2x80x9cMemory Controller Including Embedded Data Compression and Decompression Enginesxe2x80x9d and filed Jun. 5, 1995;
Ser. No. 08/916,464 titled xe2x80x9cMemory Controller Including Embedded Data Compression and Decompression Enginesxe2x80x9d and filed Aug. 8, 1997;
Ser. No. 09/241,139 titled xe2x80x9cMemory Controller Including Embedded Data Compression and Decompression Enginesxe2x80x9d and filed Feb. 1, 1999;
Ser. No. 08/565,103 titled xe2x80x9cMemory and Graphics Controller Which Performs Pointer-Based Display List Video Refresh Operationsxe2x80x9d and filed Nov. 30, 1995, which has issued as U.S. Pat. No. 5,838,334;
Ser. No. 08/770,017 titled xe2x80x9cSystem and Method for Simultaneously Displaying a Plurality of Video Data Objects Having Different Bit Per Pixel Formatsxe2x80x9d and filed Dec. 19, 1996;
Ser. No. 08/604,670 titled xe2x80x9cGraphics System Including a Virtual Frame Buffer Which Stores Video/Pixel Data in a Plurality of Memory Areasxe2x80x9d and filed Feb. 21, 1996;
Ser. No. 09/056,021 titled xe2x80x9cVideo/Graphics Controller Which Performs Pointer-Based Display List Video Refresh Operationsxe2x80x9d filed on Apr. 6, 1998;
Ser. No. 09/239,659 titled xe2x80x9cBandwidth Reducing Memory Controller Including Scalable Embedded Parallel Data Compression and Decompression Enginesxe2x80x9d whose inventors are Thomas A. Dye, Manuel J. Alvarez II, and Peter Geiger, and filed on Jan. 29, 1999.
The present invention relates to computer system graphics architectures, and more particularly to a graphics controller which performs pointer-based display list video operations to build and manipulate two and three dimensional objects and transfer the objects video data from a memory to a display device.
Since their introduction in 1981, the architecture of personal computer systems has remained substantially unchanged. The current state of the art in computer system architectures includes a central processing unit (CPU) which couples to a memory controller interface that in turn couples to system memory. The computer system also includes a separate graphical interface for coupling to the video display. In addition, the computer system includes input/output (I/O) control logic for various I/O devices, including a keyboard, mouse, floppy drive, hard drive, etc.
In general, the operation of a modern computer architecture is as follows. Programs and data are read from a respective I/O device such as a floppy disk or hard drive by the operating system, and the programs and data are temporarily stored in system memory. Once a user program has been transferred into the system memory, the CPU begins execution of the program by reading code and data from the system memory through the memory controller. The application code and data are presumed to produce a specified result when manipulated by the system CPU. The code and data are processed by the CPU and data is provided to one or more of the various output devices. The computer system may include several output devices, including a video display, audio (speakers), printer, etc. In most systems, the video display is the primary output device.
Graphical output data generated by the CPU is written to a graphical interface device for presentation on the display monitor. The graphical interface device may simply be a video graphics array (VGA) card, or the system may include a dedicated video processor or video acceleration card including separate video RAM (VRAM). In a computer system including a separate, dedicated video processor, the video processor includes graphics capabilities to reduce the workload of the main CPU. Modern prior art personal computer systems typically include a local bus video system based on either the peripheral component interconnect (PCI) bus or the VESA (Video Electronics Standards Association) VL bus, or perhaps a proprietary local bus standard. The video subsystem is generally positioned on a local bus near the CPU to provide increased performance.
Therefore, in summary, program code and data are first read from the hard disk to the system memory. The program code and data are then read by the CPU from system memory, the data is processed by the CPU, and graphical data is written to the video RAM in the graphical interface device for presentation on the display monitor. The CPU typically reads data from system memory across the system bus and then writes the processed data or graphical data back across the system bus to the I/O bus or local bus where the graphical interface device is situated. The graphical interface device in turn generates the appropriate video signals to drive the display monitor. It is noted that this operation requires data to make two passes across the system bus and/or the I/O subsystem bus. In addition, the program that manipulates the data must also be transferred across the system bus from the main memory. Further, two separate memory subsystems are required, the system memory and the dedicated video memory, and video data is constantly being transferred from the system memory to the video memory frame buffer.
One recent trend in computer system architecture and design is referred to as a xe2x80x9csharedxe2x80x9d or xe2x80x9cunifiedxe2x80x9d memory, also referred to as a unified memory architecture (UMA). In this architecture, the main or system memory is used for operating system and applications software as well as for the video frame buffer. However, one problem with the xe2x80x9cunifiedxe2x80x9d or xe2x80x9csharedxe2x80x9d memory approach is the perceived need for additional bandwidth to perform video functions such as bit block transfers and video refresh, rasterization and display of three dimensional objects, as well as CPU manipulation of programs and data within the same memory subsystem.
Current 3D display system use a method called the xe2x80x9cimmediatexe2x80x9d mode to render 3D objects. This mode draws a single triangle at a time checking a Z-buffer and reading a texture map or other source data to cover each single triangle. This prior art requires increased memory bandwidth due to triangles that are completely drawn and new triangles that overlap or hide previously drawn triangles. UMA architectures that use immediate mode 3D will be slower and lower performance due to these limitations.
Computer systems are being called upon to perform larger and more complex tasks that: require increased computing power. In addition, modern software applications require computer systems with increased graphics capabilities. Modem software applications typically include graphical user interfaces (GUIs) which place increased burdens on the graphics capabilities of the computer system. Further, the increased prevalence of multimedia applications, such as digital video and 3D graphics, also demands computer systems with more powerful graphics capabilities. Therefore, a new computer system and method is desired which provides increased system performance while reducing system cost, in particular, increased video and 2D/3D graphics performance than that possible using prior art.
The present invention comprises a video, 2D and 3D graphics controller, also referred to as the Integrated Memory Controller (IMC), which includes a novel spanning based system and method for rendering and display of 2D and 3D graphical data on a display device or video monitor, preferably using the main system memory in a unified or shared manner. The novel object based and spanning based display refresh list system for display of 2D and 3D graphical data can also be used within a graphics adapter with it""s own local memory system. The IMC performs pointer-based display list video operations for rendering of 2D and 3D video data. The graphics controller of the present invention minimizes data movement for 2D/3D and video data manipulation for video display updates and thus greatly increases system performance. The graphics system uses a list of object pointers to assemble the output display. The objects may reside in virtual locations such as memory or across LAN or WAN communication links and be of any data type (i.e. graphics, video, audio, or control) or color format. In addition, objects use a virtual addressing system for the display output which allows unrestricted movement on the display surface without actual data movement required in prior art frame buffer systems. The IMC is capable of manipulating 3D graphical data similar to streaming video sources. This makes the invention well suited for display and manipulation of environments where 3D graphics and streaming video formats are mixed. In the preferred embodiment, the IMC transfers data between the CPU local bus and system memory and also transfers data between the system memory and the video display output. The IMC may eliminate the need for one or more of a separate 2D/3D graphics, audio, video, and telephony and core logic subsystems.
The IMC uses techniques to improve overall system performance and user response time by use of the main system memory as a virtual graphical frame buffer and program/data storage. The IMC includes a unique system level architecture that reduces data bandwidth requirements for general media input/output functions. Because the host CPU is not required to move data between main memory and the graphics, audio and/or telephony subsystems as in conventional computers, data can reside virtually in the same subsystem as the main memory. Therefore, for media output data (audio, video, telephony) the host CPU or DMA master is not limited by external available proprietary bus bandwidth, thus improving overall system throughput.
The integrated memory controller (IMC) preferably includes an advanced memory controller, 2D/3D graphics, audio, video, and optionally telephony processing capabilities. The 3D graphics capabilities of the IMC include numerous significant advances that provide greatly increased performance over prior art systems. The memory controller (IMC) of the present invention may sit on the main CPU bus, (not limited to that bus) or a high-speed system peripheral bus such as the PCI or the accelerated graphics peripheral (AGP) bus. The IMC includes one or more symmetric memory ports for connecting to system memory. The IMC also includes video outputs, (where the term xe2x80x9cvideo outputsxe2x80x9d may be used to refer to display output to drive the output display device) preferably RGB (red, green, blue) outputs as well as NTSC, HDTV or PAL video plus horizontal and vertical synchronization signal outputs. These signals directly drive the video display monitor. The IMC may also include one or more video outputs, preferably (but not limited to) industry standard RGB, YUV, NTSC, PAL, HDTV and flat panel display interfaces. The IMC also may include numerous other interfaces for video, audio, Internet and/or telephony devices, among others
The IMC includes a novel system and method for manipulating and rendering 3D graphics. The IMC first operates to construct a 3-D Virtual display refresh list (3-DVDRL) in system memory. The IMC then executes the 3-D VDRL by reading the VDRL and generating and/or accessing the appropriate pixel data from system memory to construct an image or display objects. For example, execution of the 3-D VDRL causes the generated pixel data to be stored in memory as an image.
After the IMC executes the 3-D VDRL, the IMC may then create a separate 2-D VDRL which references the pixel data, and then execute the 2-D VDRL to render the pixel data on the screen. In alternate embodiments the 2-D VDRL and or 3-D VDRL may be created outside the IMC by an external CPU or computing device. Alternatively, the IMC stores the pixel data generated by execution of the 3-D VDRL in a conventional frame buffer and performs a refresh of the frame buffer to render the pixel data on the screen. The IMC may also provide the pixel data directly to a rendering engine for real time display after executing the 3-D VDRL.
The IMC operates to construct the 3-D VDRL by first parsing the 3D object and generating independent vertex-sorted geometric primitives and then performing setup on the geometric primitives. Geometric primitives may comprise trapezoids, splines, triangles, lines or points, and are generically termed polygons or triangles within this disclosure. This includes assembling a list of parameters for each of the triangle vertices and determining slope values for the triangle edges. The IMC uses 3D vertex and slope information to compute horizontal segments that make up each triangle,
The IMC then performs a Y sort of the triangles for each span line, and an X sort of triangles segments and vertices for each span line. The Y sort operates to sort triangles by minimum Y position as well as the minimum Y vertex for each triangle. For each span line, triangle segments are generated and X sorted based on starting X position of triangles for each segment. Span lines are horizontal line of pixels that run the entire length of the display device and segments are portions of the span line that represent horizontal triangle start to stop segments for a respective triangle. After the Y and X sorts, the IMC performs a Z rules determination for each span line. The Z rules determination, determines the segments that are visible, and discards those segments that are hidden, i.e., is used to reject the now one-dimensional triangle segments that are hidden by other triangle segments.
The IMC or attached CPU then constructs a 3-D VDRL list for each span line comprising pointers which reference viewed triangle spans. The 3-D VDRL comprises pointers which reference viewed triangle spans. Thus, the 3D geometry is flattened to a one dimensional set of triangle segments for a plurality of triangles and a plurality of span lines, and the information for source textures, position, and 3D attributes is stored within the 3-D VDRL.
The 3-D VDRL is then executed. More specifically, the 3-D VDRL is read and interpreted for triangle parameter data, texture address, attributes and other control information. The 3D graphics engine then renders all the triangle segments for multiple triangles for an entire span line as indicated in the 3-D VDRL. During execution of the 3-D VDRL, the 3-D VDRL is fetched for instructions and pointers to control the rasterization of the output image by the 3D engine. Execution of the 3-D VDRL may cause rasterization of the output image to the memory on to the display device.